With semiconductor memory devices, one differentiates between so-called functional memory devices (e.g. PLAs, PALs, etc.), and so-called table memory devices, e.g. ROM devices (ROM=Read Only Memory), and RAM devices (RAM=Random Access Memory or write-read memory).
A RAM device is a memory for storing data under a predetermined address and for reading out the data under this address later.
The corresponding address may be input in the RAM device via so-called address input pins. For inputting and outputting the data, a plurality of, e.g. 16, so-called data in-put/out-put pins (I/Os or Inputs/Outputs) are provided. By applying an appropriate signal (e.g. a Read/Write signal) to a write/read selection pin, the user can select whether the data is stored or read.
It is advantageous to accommodate as many memory cells as possible in a RAM device. In the case of so-called SRAMs (SRAM=Static Random Access Memory), the individual memory cells consist of few, for instance 6, transistors, and in the case of so-called DRAMs (DRAM=Dynamic Random Access Memory) the individual memory cells usually consist of a signal, correspondingly controlled capacitor, with the capacitance of which one bit each can be stored as charge. This charge, however, remains for a short time only. Therefore, a so-called “refresh” must be performed regularly, e.g., approximately every 64 ms.
For technological reasons, the individual memory cells in memory devices, in particular DRAM devices, are arranged (e.g., positioned side by side in a plurality of rows and columns) in a rectangular matrix (regularly divided into a plurality of cell fields) or in a rectangular array (regularly divided into a plurality of cell fields).
In order to obtain a correspondingly high total storage capacity, and/or to achieve a data read or write rate as high as possible, instead of one single array, there by be provided a plurality of, e.g. four substantially rectangular, individual arrays in one single RAM device or chip (“multi-bank chip”). The plurality of arrays are called “memory banks”.
In order to perform a write or read access, a particular, predetermined sequence of instructions must be performed: For instance, by means of a word line activating instruction (ACT), a corresponding word line, assigned to a particular array (and defined by the row address), is initially activated.
As a result, the data values stored in the memory cells assigned to the corresponding word line are read by the sense amplifiers assigned to the corresponding word line. This is called the “activated state” of the word line.
Subsequently, by means of an appropriate read (RD) or write (WT) instruction, the corresponding data, which is specified by the corresponding column address, are output by the corresponding sense amplifier(s) assigned to the bit line specified by the column address (or vice versa, where the data are read into the corresponding memory cells).
Next, by means of a word line deactivating instruction (e.g., a precharge PRE instruction), the corresponding word line is again deactivated, and the corresponding array is prepared for the next word line activating instruction (ACT).
The above-mentioned sense amplifiers are each arranged in a sense amplifier region positioned between two cell fields, wherein, for reasons of space, each sense amplifier may be assigned to two different cell fields (namely, the two cell fields directly adjacent to the corresponding sense amplifier region). These are called shared sense amplifiers.
Depending on whether data are to be read from the cell field positioned at the left or at the right, next to the respective sense amplifier (or the cell field positioned above or below the respective sense amplifier), the corresponding sense amplifier is connected to the corresponding cell field by appropriate switches. In particular, the corresponding sense amplifier is connected to the corresponding bit line assigned to the respective cell field, or is connected electrically with the corresponding cell field, in particular the corresponding bit line assigned to the respective cell field. The corresponding sense amplifier may alternatively be disconnected from the corresponding cell field (or the corresponding bit line assigned to the respective cell field), or may be disconnected electrically from the corresponding cell field or the corresponding bit line assigned to the respective cell field.
The corresponding switches effecting the connecting or disconnecting, respectively, in particular transistors, are controlled by an appropriate control line (MUX lines, in particular a right MUX line (MUXR line) and a left MUX line (MUXL line)) positioned parallel to the word lines at the left or at the right next to the cell fields in the above-mentioned sense amplifier regions (and above or below regions adjacent thereto).
The control signals (MUXR or MUXL signal) applied at the MUX lines are driven by a driver device connected with the corresponding MUX line, said driver device being arranged in a region positioned below or above (or at the right or at the left of) all of the cell fields of the corresponding array, e.g., a segment control region positioned at an edge region of the array.
The MUX lines may be relatively long. This results in relatively large signal delays of the control signals (MUX signals) applied at the MUX lines, and to a relatively low switching rate during the connecting and/or disconnecting of the sense amplifiers to or from the corresponding cell field (or the bit line assigned to the corresponding cell field).